Intel P55: What we know so far
Lynnfield and Havendale don’t have their name right now, but Intel’s Ibex Peak have just got its name “P55″ from Intel’s new roadmap.
Of course, that P55 shows up in the roadmap doesn’t mean P45 is becoming outdated. In November there will be three Core i7 CPU hit the market, but that’s enthusiast market, We believe that P45 will still be the leader until P55 shows up in third quarter next year.
P55 chipeset will be single chip design, that means there won’t be any ICH chips anymore. We’ve already seen this kind of design before, the recently launched MCP7A is one of the many. But Intel is still new will this kind of chip design in mainstream-performance market. Hope the integration won’t lead to performance loss.
In one of the P55 document Intel saids P55 will be pin capable to other 5 series chipset, this means if manufacturer wants, then a single PCB can support multiple chipsets.
One of the interesting features of P55 chipset is there is a thermal sensor built in, so we can monitor its thermal status like it is a CPU.
P55 specs:
Socket: LGA 1160, Lynnfield and Havendale supported.
PCIe 2.0: Dual graphic card supported, Single card runs with 1×16, dual card run with 2×8.
USB: P55 integrated USB Rate Match Hub, supports as much as 14 USB 2.0 slot.
SATA: 6xSATA 3.0Gb/s，With Intel Matrix Storage Technology 9.0, P55 supports RAID 0/1/5/10.
Till now, we don’t have any good news on P55 supporting USB 3.0. Maybe it is still too early?
October 21st, 2008 at 11:07 pm
“P55 chipeset will be single chip design, that means there won’t be any ICH chips anymore. We’ve already seen this kind of design before, the recently launched MCP7A is one of the many. But Intel is still new will this kind of chip design in mainstream-performance market.”
Please notice that the functions of the north bridge (x16 PCI express, memory controller, integrated graphics) are _all_ now on the processor package. Note also that the P55 talks to the processor via DMI. Does this remind you of the current ICH10? It should. The P55 PCH is essentially just the southbridge, which is _already_ a single chip.
Likewise, if you look at the block diagram of Havendale, the dual-core LGA 1160 desktop Nehalem coming next year, the GMCH that carries the IGP, memory controller, DMI link and PCI Express x16 controller is actually a separate die from the processor and uses QuickPath internally on the processor package to communicate with it. Does this remind you of the current G45 MCH? It should, since what you have is an IGP-equipped northbridge talking to the processor die via QuickPath instead of the FSB — the functions are the same.
Lynnfield integrates the memory controller, PCI Express x16 controller and DMI link on the same die as the four processor cores, so it’s schematically different from Havendale.
October 21st, 2008 at 11:25 pm
To see what I’m talking about, see this diagram off PC Watch:
http://pc.watch.impress.co.jp/docs/2008/0602/kaigai03l.gif
(Source: http://pc.watch.impress.co.jp/docs/2008/0602/kaigai442.htm)
In particular look at the Lynnfield and Havendale block diagrams at the bottom of the graphic. On the Havendale diagram, the die whose functionality is shown with a green background is effectively the full northbridge, including the memory controller, which is obviously _not_ integrated with the processor die; the dies talk using QuickPath in the same way current Core 2 processors talk to their MCH/GMCH via the FSB.
Similarly, note how all the functionality of the northbridge is now on the processor package, which leaves only the southbridge functionality to be implemented on the Platform Controller Hub (PCH), which is what the P55 is.
Bloomfield, Nehalem-EP and Nehalem-EX are different from the above again, because they do not have the PCI express controller (which is what is “north of PCI”, hence the defining northbridge component). Hence they have their IOH (I/O Hub), the X58 Tylersburg, which functions much the same way as the chipsets on AMD’s K8, K10 and K10.5 platforms do — its primary purpose is implementing the PCI Express lanes, and it links to the southbridge much like AMD’s 7×0 chipsets do. It also talks to the processor the same way AMD’s chipsets do, using QuickPath rather than its analogue, HyperTransport.
So, in summary:
* The architecture of Nehalem-EX, Nehalem-EP and Bloomfield (effectively a single-processor version of Nehalem-EP) is like AMD’s K8, K10 and K10.5, with the memory controller integrated on the processor die and the I/O controllers still in a separate northbridge to which it talks via a point-to-point link. Peripherals are on their own I/O Controller Hub (ICH).
* Lynnfield’s architecture is _unique_ in that it integrates the entire northbridge functionality onto the processor die, including the PCI Express controller. It is the most integrated Nehalem-generation processor that Intel is going to launch. It talks to its southbridge that carries integrated peripherals via DMI. The southbridge is the P55 PCH and similar vPro ?Q-series (Piketown/Piketon) and Viiv ?G-series (Kingscreek) PCH derivatives.
* Havendale’s _logical_ architecture is analogous to the current Core 2 Duo, in that the processor die only carries the cores and cache; it talks to the memory controller, PCI Express x16 controller and IGP over QuickPath, albeit within the same processor package. The GMCH die on the processor package then talks to the southbridge (P55 et al) via DMI, much like the current P43/P45/G43/G45/Q43/Q45/X48 talk to their ICH9R/ICH10/ICH10R/ICH10DH/ICH10DO via DMI.