GTX460 Specs Totally Exposing or that Will be the Local Point of Feimi

Last week, we have lanuched some specs about NVIDIA GeForce CTX460, 336 CUDA Core, memory for the 192bit 768MB.

Today we got one sectional drawing about GTX460, which we can get more information. Such as, frequency. Spec for Core / Shader /memory frequency respectively 675/1350/1800MHz, higer than GTX465(608/1215/1604MHz).

Though memory capacity, bandwidth specifications lower than GTX465, its performance will weaker than GTX465, but overall its very close. What’s more, it has OC that emphasized before, the main core is it has about 13W TDP, and GTX465 is 150W.

And its price will much lower than GTX465, be pricing at $230.

In addition, there could be presumed CUDA Core, 256bit 1GB of memory for the later, its performance may pass GTX465. Does NVIDIA make some changing in specs to balance its performance? We do not know yet, just wait.

10 Responses to “GTX460 Specs Totally Exposing or that Will be the Local Point of Feimi”

  1. JeeBee Says:

    336 CUDA cores? I thought Fermi had a granularity of 32 CUDA cores per “group of shaders” – that 226 number doesn’t work out, it’s 10.5 groups.

    Is this GF104? Does GF104 reduce the granularity to 16 CUDA cores therefore? GF104 is 24 groups of 16 cores (=386 CUDA cores in total), and the 460 has three groups disabled for yield reasons.

  2. Cornolio Says:

    Hahahahahahaha, nice vga next gtx 450 (cuda 225,25 cores) hahaha

  3. FPN Says:

    13W has to be a typo. There’s no way.

  4. Dynamic Says:

    U know everthing is possible.

  5. 94xj Says:

    This just doesn’t make sense. GF100 goes in groups of 32 as said previously…and I just bought a 465 for less than $250

  6. ted Says:

    Why did you buy a 465

  7. colin Says:

    In terms of hardware, 336 “CUDA cores” *probably* means 14 SM’s (and that is what the device has) each with 24 SP’s instead of 32, and probably 3 special instruction units instead of 4.

    The SP’s are arranged in 4 groups of 8 on the chip, and each group of 8 has a special instruction unit and a scheduler etc etc.

    In other words, they’ve made the power saving by turning off 1/4 of the execution units (removing one of these groups of 8 on the SM) in each SM on the chip.

    This lowers the transistor count, so it’s cheaper. What happens to the cache’s and so on I don’t know. Hopefully they stay the same as usual. but it’s asymmetric, which seems problematic

    the special number “32″ is the warp size; threads are in theory (i.e. in software terms) executed in groups of 32 to match the SP number. In practice, what physically happens is that a half warp is scheduled at a time on a FERMI, and I think a quarter warp on the old ones, but the hardware is very different and it’s hard to really compare. but scheduling half a warp on a device with 24 SP’s would appear to leave 8 threads idle. I guess they’ve thought about it….these are not simple devices. I’m doing my best to understand them myself, and it’s my job!

    this is of course just my guess as to what they’ve done, based on past behavior and the architicture spec for FERMI.

    anyway, that’s what’s happening in hardware terms, and why the power consumption is lower and they cost less. It’s just a “crippled” FERMI.

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