JEDEC Updates High Bandwidth Memory Standard

Last year AMD brought up a new revolution on graphics card by first adpoting High Bandwidth Memory (HBM) for its Fiji GPU. And JEDEC, the leader in development of standards for the microelectronics industry, has today announced an even more impressive DRAM standard – JESD235 High Bandwidth Memory.

 

JESD235A leverages Wide I/O and TSV technologies to support up to 8 GB per device at speeds up to 256 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack.  The standard supports 2-high, 4-high and 8-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1GB–8GB per stack.

 

Additional improvements in the recent update include a new pseudo channel architecture to improve effective bandwidth, and clarifications and enhancements to the test features.  JESD235A also defines a new feature to alert controllers when DRAM temperatures have exceeded a level considered acceptable for reliable operation so that the controller can take appropriate steps to return the system to normal operation.

The company didn’t mention when the new standard make a debut, but earlier reports claimed AMD and NVIDIA are both using HBM 2 for their next-gen flagship products, which should be arriving late 2016.

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